VU9P/13P FPGA up to 800GbE
The total transceiver delay (Rx+Tx) is about 20ns
It is the ideal interface for high-frequency trading (HFT)/Fintech
AiNET-DD4 provides a large Xilinx FPGA on a 3/4 length PCle board with a QSFPDD (Double density) cage for maximum port density. Using the Virtex UltraScale+ VU13P or VU9P FPGA, the board supports up to 8x100GbE.
Xilinx VU9P/13P FPGA
4 QSFP-DD interfaces, up to 8 x100GbE Up to 512GBytes DDR4 SDRAM Up to 3.8M logical units.
HFT
Fintech